1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device including a charge pump circuit for generating a predetermined internal voltage from an externally applied power supply voltage.
2. Description of the Background Art
Semiconductor devices such as flash memories that carried out data writing, reading, and erasing electrically generate internally a plurality of voltages other than the externally applied power supply voltage to carry out the above operations according to these internal voltages. For example, a flash memory has a memory cell formed by one transistor, wherein a drain is connected to a bit line and a control gate is connected to a word line. In an erasing operation, a positive high voltage is applied to a control gate of a transistor serving as a memory cell, and a negative high voltage is applied to a source and a P well thereof, whereby electrons are injected into a floating gate taking advantage of tunneling phenomenon. In a writing operation, a negative high voltage is applied to the control gate, and a positive high voltage is applied to the drain, whereby electrons are drawn out from the floating gate according to tunneling phenomenon.
Various internal voltages used in each operation of a conventional flash memory will be described hereinafter. FIG. 11 is a diagram for explaining voltages applied to memory cells in selected and de-selected sectors under various operations of a flash memory.
Referring to FIG. 11, a source voltage Vs is -8V, a control gate voltage Vcg is 10V, a P well voltage BG is -8V, and a drain voltage Vd is floating, for example, in an erasing operation. In the following, a memory cell of a selected sector and a de-selected sector has predetermined voltages applied including a source voltage Vs, a control voltage Vcg, a drain voltage Vd, and a P well voltage BG to carry out respective operations as shown in FIG. 11. When there is only a single externally applied power supply voltage, for example only 3V, a positive voltage generation circuit and a negative voltage generation circuit generally include a charge pump circuit for generating various voltages of 6V, 10V, 4V, -8V, and -4V on the basis of the single power supply voltage.
A positive voltage generation circuit and a negative voltage generation circuit used in the above-described conventional flash memory will be described hereinafter with reference to the drawings. FIG. 12 shows a structure of a conventional positive voltage generation circuit.
Referring to FIG. 12, a positive voltage generation circuit includes a positive voltage charge pump circuit 101, an oscillator 102, a drive circuit 103, and a Zener diode D1.
Positive voltage charge pump circuit 101 includes NMOS transistors Q201-Q212, and capacitors C201-C210. Transistors Q201-Q210 are diode-connected, and also connected to capacitors C201-C210.
Oscillator 102 receives a control signal OSC to provide a clock signal of a predetermined frequency to drive circuit 103. Drive circuit 103 responds to a clock signal from oscillator 102 to provide clock signals .phi.p and /.phi.p ("/" implies an invert signal) complementary to each other. Positive voltage charge pump circuit 101 has a node N1 charged to V.sub.CC -V.sub.th (V.sub.CC is power supply voltage, and V.sub.th is threshold voltage of transistor), which is then raised in response to clock signal .phi.p. Next, transistor Q201 is turned on, whereby the potential of a node N2 rises. When, clock signal /.phi.p attains a H level (logical high), the potential of node N2 further rises. As a result, positive voltage charge pump circuit 101 can generate a voltage higher than a power supply voltage V.sub.CC by sending charges in capacitors C201-C210 sequentially to a succeeding stage. The generated high voltage V.sub.PP is clamped at a predetermined potential by Zener diode D1. According to the above-described operation, a high voltage V.sub.PP greater than power supply voltage V.sub.CC can be output at a predetermined potential level in response to control signal OSC. By using such a positive voltage generation circuit, a conventional flash memory carries out various operations of a memory cell according to internally generated voltages from a power supply voltage V.sub.CC.
A conventional negative voltage generation circuit will be described hereinafter with reference to FIG. 13 showing a structure thereof.
Referring to FIG. 13, a negative voltage generation circuit includes a negative voltage charge pump circuit 104, an oscillator 105, a drive circuit 106, and a Zener diode D2. Negative voltage charge pump circuit 104 includes PMOS transistors Q221-Q231, and capacitors C221-C230.
Transistors Q221-Q230 are diode-connected, and also connected to capacitors C221-C230.
Oscillator 105 and drive circuit 106 operate in a manner similar to oscillator 102 and drive circuit 103 of FIG. 12. Complementary clock signals .phi.n and /.phi.n are provided to negative voltage charge pump circuit 104. Similar to the operation of the above-described positive voltage charge pump circuit, negative voltage charge pump circuit 104 provides a negative voltage NV.sub.PP which is clamped at a predetermined voltage level by Zener diode D2. By means of such a negative voltage generation circuit, a conventional flash memory supplies predetermined negative voltages, for example, to a memory cell according to respective operation modes.
Conventional positive and negative voltage generation circuits had problems set forth in the following since a voltage generated from a charge pump circuit is clamped at a predetermined level by a clamping voltage of a Zener diode.
The clamping voltage of a Zener diode is too fluctuating as a result of incidental variations in the manufacturing process thereof. Therefore, a desired positive voltage or a negative voltage could not be provided accurately. Furthermore, an output clamp could not be achieved if the current flow is too low in a clamping operation by a Zener diode. Therefore, this imposed a great load on a charge pump circuit having the current supplying ability limited. There was a also problem of increasing the cost due to a dedicated mask required in forming a Zener diode on a semiconductor substrate.
FIG. 14 is a diagram showing structures of a Zener diode and a P channel transistor. In a clamping method using a Zener diode, it is necessary to set the injection amount towards a P.sup.+ diffusion layer according to a desired clamping level since the voltage to be clamped varies on the basis of the junction characteristic of a Zener diode. For example, when a Zener diode is formed by a PN junction of a P.sup.+ diffusion layer and an N well layer, the injection amount into the P.sup.+ diffusion layer must be specified so that a desired breakdown voltage is obtained. However, this injection amount differs from that towards a P.sup.+ diffusion layer of a p channel transistor. It is therefore necessary to provide injection differing in amount towards the P.sup.+ diffusion layers of a P channel transistor and a Zener diode by means of an additional mask for P.sup.+ injection for a Zener diode. This additional mask for forming a Zener diode results in increasing the complexity of the manufacturing process and the cost thereof.